1. Field of the Invention
The present invention relates to an operation processing apparatus used in data driven type processors and the like having a circular pipeline, and more particularly, to an operation processing apparatus for carrying out at high speed the process of a feedback loop included in a digital filter and the like.
2. Description of the Related Art
FIG. 1 is a signal flow graph of a 1-st order IIR (Infinite Impulse Response) filter as an example of a digital filter. The digital filter is a digital circuit including an adder element, a delay (generation increment) element, and a multiplier element. The digital filter shown in FIG. 1 includes adder elements 52 and 58, a delay element 54 for generation increment, and multiplier elements 56, 60 and 62.
FIG. 2 is a signal flow graph of the feedback loop functioning as a critical path in the flow graph of FIG. 1. Referring to FIG. 2, the feedback loop includes an adder element 52, a delay element 54, and a multiplier element 56. The operation result of one preceding generation having a factor of -B1 multiplied by multiplier element 56 is added to a fed data .mu. to be provided to a subsequent process as an output .theta. as well as to delay element 54. Delay element 54 holds the operation result and provides the operation result of one preceding generation to multiplier element 56.
When the digital filter of FIG. 1 is realized using a data driven type processor having a circular pipeline, the process is carried out as follows. Upon provision of both a fed data and a history value with respect to an input of one preceding generation from multiplier element 56, an addition instruction is executed. The added result output to the circular pipeline is provided to a subsequent process as the result of a feedback loop process, and also to the circular pipeline as an input for the next generation increment operation. In response, a generation increment operation is carried out. The result is output to the circular pipeline and then fed as an input of the next multiplication operation. When the result of a generation increment operation is fed, a multiplication process with the factor of -B1 is executed, whereby the result is output to the circular pipeline. This value becomes one of the input data for the addition operation in the next feedback loop execution via the circular pipeline.
According to this conventional art, the three operations shown in FIG. 2 (addition, generation increment, multiplication) are carried out by circulating subsequently the circular pipeline. It is therefore necessary to circulate the circular pipeline at least three times for one feedback loop operation. If the time required to circulate the circular pipeline once is 1.mu. seconds, the time required for one feedback loop operation is 3.mu. seconds. Data cannot be fed from the input portion during this time period, so that a digital filter process of high speed was not possible.
Such a data driven type processor is generally provided with a multiplication unit for carrying out multiplication process and an arithmetic logic operation unit for carrying out arithmetic logic operation.
FIG. 3 is a circuit block diagram of a multiplication unit used in the operation processing apparatus of a conventional data driven type processor. Referring to FIG. 3, the multiplication unit includes a decoder 40a, data latch circuits 32a, 34a, 36a, 38a, a multiplier 46a provided between data latch circuits 36a and 38a, and a data selector 48a connected to the output of data latch circuit 38a. The multiplication unit also includes transfer control elements C1-C4 for controlling the operation timing of each data latch circuit for properly carrying out a pipeline process.
The multiplication unit shown in FIG. 3 operates as follows. Right data and left data for a multiplication process and an instruction code indicating an instruction to be executed are provided to the multiplication unit. Decoder 40a decodes the instruction code to provide the same to data latch circuit 32a. The right data, the left data, and the decoded instruction code are subsequently transferred to data latch circuits 34a and 36a according to a reception request signal and a transmission permission signal transferred between one of transfer control elements C1-C3 and a preceding/succeeding transfer control element.
The right data provided from data latch circuit 36a is supplied to multiplier 46a. The left data provided from data latch circuit 36a is supplied to multiplier 46a and to data latch circuit 38a. Multiplier 46a multiplies the respective n bits of right data by the left data to provide the multiplied result of 2n bits to data latch circuit 38a. The instruction code is provided from data latch circuit 36a to data latch circuit 38a. Data latch circuit 38a responds to a clock signal from transfer control element C4 to hold the respective input data which are provided to data selector 48a.
Data selector 48a responds to a decoded instruction code provided from data latch circuit 38a to select either the left data provided from data latch circuit 38a or the multiplication result of multiplier 46a to provide the same as data of 2n bits to a subsequent shift circuit and a tag processor not shown.
In an operation processing apparatus of a conventional data driven type processor, only one operation was executable during one circulation of the circular pipeline. Data must circulate the circular pipeline several times in order to execute the above-described feedback loop. Data cannot be fed from an input unit during this time period, impracticable of high speed operation process of the feedback loop.